Call for Proposals: Accelerator for Advanced Strained Silicon on Insulator Substrates

Scope

• The proposed accelerator should address all levels of the key technological steps required to bring sSOI substrates to industrial scale:
  • Development of industrial-grade sSOI substrates will focus on achieving low defect density, crucial for enhancing electron mobility and ensuring high-performance FD-SOI devices at the 7 nm node. This will involve refining strain engineering techniques, particularly to introduce a uniform global strain that can balance the performance for strained NMOS and relaxed PMOS transistors.
  • Ensure compatibility with existing semiconductor manufacturing, the accelerator will refine process integration and optimisation. This includes improving epitaxial growth, wafer bonding, and defect reduction techniques to meet the requirements of advanced FD-SOI production processes.
  • Finally, the accelerator will promote collaboration across the semiconductor ecosystem, working with other pilot lines, as well as connecting to the design platform and competence centres, among others.

Funding Information

• Budget (EUR) – Year 2025: 30 000 000
• Contributions: 1000000 to 30000000

Expected Outcomes

• The proposed accelerator shall be established with all the necessary equipment and facilities, and will target the following main objectives:
  • Develop industrial-grade sSOI substrates with reduced defect density to improve electron mobility and overall device performance. These substrates should be capable of addressing the market entry of 7nm FD-SOI expected by 2030 as well as be fully compatible with existing FD-SOI technologies, including 22FDX and 18nm FD-SOI.
  • Develop scalable and cost-effective manufacturing processes, ensuring compatibility with current industrial standards and promoting widespread adoption.
  • Demonstrate the feasibility of integrating strained NMOS and relaxed PMOS areas, balancing the performance of both transistors.
  • Accelerate the transition from R&D to industrial-scale production by providing a pre-industrial infrastructure capable of producing several thousand wafers per year.
  • Develop demonstrators to validate the benefits of sSOI-based FD-SOI over competing FinFET technologies, particularly in terms of improved RF performance, lower noise, and reduced power consumption.
  • Enable open access to Process Design Kits (PDKs) and design building blocks to foster the differentiation of FD-SOI technology, including stress and relaxation design elements.
  • Enable early-stage design and system-level integration of sSOI substrates through MultiProject Wafer (MPW) runs, allowing timely validation of substrate performance in real-world applications. Support design efforts for high-speed broadband RF circuits, mm-Wave radar systems, and compact low power automotive and IoT solutions as part of the Next Gen FDSOI roadmap.

Eligibility Criteria

• Specific eligibility conditions:
  • Size limit: 70 Participants
  • Max EU Contribution per partner (% of the total EU funding): 50 %
• For the partners of a Participating State that coordinates grants, specific rules may apply regarding the eligibility to national funding.
• Subject to participation restrictions for the protection of European digital infrastructures, communication and information systems, and related supply chains.
• Legal entities that are established in the Union or EEA countries but are controlled from third countries may only participate on the condition that they guarantee the protection of the essential security interests of the Union and the Member States and that they ensure the protection of classified documents information. Where applicable, security guarantees need to be provided after proposal selection.

For more information, visit EC.